Reconfigurable architecture refers to modules (VPUs) having a configurable function and/or interconnection, in particular integrated modules having a plurality of one-dimensionally or multidimensionally arranged arithmetic and/or logic and/or analog and/or memory and/or interconnecting modules (hereinafter referred to as PAEs) and/or communicative/peripheral modules (IOs) that are interconnected directly or via one or more bus systems. PAEs are arranged in any configuration, combination, and hierarchy. This system is referred to below as a PAE array or PA.
The generic class of such modules includes in particular systolic arrays, neural networks, multiprocessor systems, processors having a plurality of arithmetic units and/or logic cells, interconnection and network modules such as crossbar switches, as well as conventional modules of the generic types FPGA, DPGA, XPUTER, etc. In this connection, reference is made in particular to the following applications of the same applicant: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT/DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516, EP 01 102 674.7, DE 102 06 856.9, 60/317,876, DE 102 02 044.2, DE 101 29 237.6-53, DE 101 39 170.6. These are herewith incorporated to the full extent for disclosure purposes.
In addition, it should be pointed out that the methods to be described here may be used for groups of multiple modules. Nevertheless, reference is made below to a VPU and/or to “modules.” These modules and their operations are to be further improved.